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Z86C93 CPS DC-4020-12
CUSTOMER PROCUREMENT SPECIFICATION
Z86C93
CMOS Z8(R) MULT/DIV MICROCONTROLLER
GENERAL DESCRIPTION
The Z86C93 is a CMOS ROMless Z8 microcontroller enhanced with a hardwired 16-bit x 16-bit multiplier, 32-bit/16-bit divider, and three 16-bit counter timers (see Functional Block Diagram). A capture register and a fast decrement mode are also provided. It is offered in 40-pin PDIP, 44-pin PLCC, 44-pin QFP, and 48-pin VQFP packages. The Z86C93 is functionally compatible with the Z86C91, yet it offers a more powerful mathematical capability. In the PDIP package, the Z86C93 is fully pin compatible with the Z86C91. In the PLCC package, the Z86C93 is also pin compatible to the Z86C91, with the addition of four signals (SCLK, /IACK, /SYNC, and /WAIT). The /WAIT signal is only available on the 25 MHz and 33 MHz devices. The Z86C93 provides up to 16 output address lines permitting an address space of up to 64 Kbytes of data and program memory each. Eight address outputs (AD7-AD0) are provided by a multiplexed, 8-bit, Address/Data bus. The remaining 8 bits can be provided by the software configuration of Port 0 to output address bits A15-A8. There are 256 registers located on chip and organized as 236 general-purpose registers, 16 control and status registers, one reserved register, and up to three I/O port registers. The register file can be divided into 16 groups of 16 working registers each. Configuration of the registers in this manner allows the use of short format instructions; in addition, any of the individual registers can be accessed directly. There are an additional 17 registers implemented in the Expanded Register File in Banks D and E. Two of the registers may be used as general-purpose registers, while 15 registers supply the data and control functions for the Multiply/Divide Unit and additional Counter/Timer blocks.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
DC-4020-12
(2-16-94)
1
Z86C93 CPS DC-4020-12
GENERAL DESCRIPTION (Continued)
/WAIT (25 MHz & 33 MHz Devices Only.) /RESET
XTAL
Output Input
VCC GND
Port 3
Machine Timing, Emulation and Instruction Control
UART
ALU
Three 16-Bit Counter/Timers
FLAGS
32 / 16 Divider
Register Pointer Register File 256 x 8-Bit Program Counter
16 x 16 Multiplier
Interrupt Control
Port 2
Port 0
4 I/O (Bit Programmable)
4
R//W
Port 1
8 Address/Data
Address or I/O (Nibble Programmable)
Functional Block Diagram
2
/SYNC
SCLK
IACK
/DS
/AS
Z86C93 CPS DC-4020-12
PIN CONFIGURATION
XTAL1 XTAL2 SCLK P30 P37 P27 +5V P36
VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16
6 5 4
3
2
1
44 43 42 41 40 39 38 37 36
P31
P26 P25
/RESET R//W /DS /AS P35 GND P32 P00 P01 P02 IACK
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
NC P24 P23 P22 P21 P20 P33 P34 P17 P16 P15
Z86C93 MCU
35 34 33 32 31 30 29
Z86C93 10 DIP
11 12 13 14 15 16 17 18 19 20
P03
P04
P05 P06 P07
P10 P11
P12 P13
P17 P16
P15 P14 P13 P12 P11 P10
44-Pin PLCC Package (20 MHz)
40-Pin DIP Package (20 MHz)
NC P24
P23 P22 P21 P20 P33 P34
P17 P16 P15
NC P24 P23
P22 P21 P20 P33 P34
P15
33 32 31 30 29 28 27 26 25 24 23 P25 P26 P27 P31 P36 +5V XTAL2 XTAL1 P37 P30 SCLK 34 35 36 37 38 39 40 41 42 43 44 12 345 6 7 8 9 10 11 22 21 20 /SYNC P14 P13 P12 P11 P10 P07 P06 P05 P04 P03
P25 P26 P27 P31 P36 NC +5V XTAL2 XTAL1 P37 P30 SCLK 37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 123 456 7 8 9 10 11 12 /SYNC P14 P13 P12 P11 P10 P07 NC P06 P05 P04 P03
Z86C93 MCU
19 18 17 16 15 14 13 12
Z86C93 MCU
/DS /AS P35 GND
P32
P00 P01
/RESET R//W
44-Pin QFP Package (20 MHz)
NC /RESET R//W
/DS /AS P35 GND
P01 P02 IACK
48-Pin VQFP Package (20 MHz)
P02 IACK
P32
P00
NC
P14 /SYNC
3
Z86C93 CPS DC-4020-12
PIN CONFIGURATIONS (Continued)
SCLK P30 P37 XTAL1 XTAL2
VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P14 P13 P12 P11 P10
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36
+5V P36 P31
P27 P26 P25
/RESET R//W /DS /AS P35 GND P32 P00 P01 P02 IACK
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/WAIT P24 P23 P22 P21 P20 P33 P34 P17 P16 P15
Z86C93 MCU
35 34 33 32 31 30 29
Z86C93 DIP
31 30 29 28 27 26 25 24 23 22 21
P03 P04 P05 P06 P07
P10 P11 P12 P13
44-Pin PLCC Package (25 MHz and 33 MHz)
40-Pin DIP Package (25 MHz and 33 MHz)
/WAIT P24 P23 P22 P21 P20 P33 P34
/WAIT P24 P23 P22 P21 P20 P33
P34
P17 P16
P15
36 35 34 33 32 31 30 29 28 27 26 25
33 32 31 30 29 28 27 26 25 24 23 P25 P26 P27 P31 P36 +5V XTAL2 XTAL1 P37 P30 SCLK 34 35 36 37 38 39 40 41 42 43 44 12 22 21 20 19 18 17 16 15 14 13 12 /SYNC P14 P13 P12 P11 P10 P07 P06 P05 P04 P03
Z86C93 MCU
P25 P26 P27 P31 P36 NC +5V XTAL2 XTAL1 P37 P30 SCLK
37 38 39 40 41 42 43 44 45 46 47 48 123
P17 P16 P15 NC
P14 /SYNC
24 23 22 21 20 19 18 17 16 15 14 13
Z86C93 MCU
/SYNC P14 P13 P12 P11 P10 P07 NC P06 P05 P04 P03
345
6 7 8 9 10 11
456
7 8 9 10 11 12
NC /RESET R//W /DS /AS P35 GND
/DS /AS P35 GND
P32
P00
P01 P02 IACK
P32
/RESET R//W
44-Pin QFP Package (25 MHz and 33 MHz)
48-Pin VQFP Package (25 MHz and 33 MHz)
4
P00 P01 P02 IACK
Z86C93 CPS DC-4020-12
ABSOLUTE MAXIMUM RATINGS
Symbol Description VCC TSTG TA Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max +7.0 +150 Units V C C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
* Voltages on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram).
I OL
DUT Device Under T est V Commutation
50 pf
I OH
Test Load Diagram
5
Z86C93 CPS DC-4020-12
DC ELECTRICAL CHARACTERISTICS VCC = 3.3V 10%
Sym VCH VCL VIH VIL VOH VOH VOL VRH VRl IIL IOL IIR ICC ICC1 ICC2 IAL
Note:
Parameter Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage
TA = 0C to +70C Min Max 0.8 VCC -0.03 0.7xVCC -0.3 7 VCC 0.1xVCC VCC 0.1xVCC
Typical at 25C
Units V V V V V V V V V V A A A mA mA A A
Conditions IIN 250 A Driven by External Clock Generator Driven by External Clock Generator
Output High Voltge 1.8 Output High Voltage VCC -100mV Output Low Voltage Reset Input High Voltage 0.8xVCC Reset Input Low Voltage -0.03 Input Leakage Output Leakage Reset Input Current Supply Current -2 -2
0.4 VCC 0.1xVCC 2 2 -180 30 12 8 10
IOH= -1.0 mA IOH = -100 A IOL = +1.0 mA
20 8 1 5
Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 25 MHz [1] HALT Mode VIN = OV, VCC @ 25 MHz [1] STOP Mode VIN = OV, VCC [1]
Standby Current (HALT Mode) Standby Current (HALT Mode) Auto Latch Current -10
[1] All inputs driven to 0V, or Vcc and outputs floating.
6
Z86C93 CPS DC-4020-12
DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10%
Sym VCH VCL VIH VIH VIL VOH VOH VOL VRH VRl IIL IOL IIR ICC Parameter TA = 0C to +70C Min Max 7 VCC 0.8 VCC VCC 0.8 Typical at 25C Units V V V V V V V V V V V A A A mA mA mA mA mA mA A A Conditions IIN 250 A Driven by External Clock Generator Driven by External Clock Generator
Max Input Voltage Clock Input High Voltage 3.8 Clock Input Low Voltage -0.03 Input High Voltage (P0,P1,P2) 2.0 Input High Voltage (P3) 2.2 Input Low Voltage -0.3 Output High Voltge 2.4 Output High Voltage VCC -100mV Output Low Voltage Reset Input High Voltage 3.8 Reset Input Low Voltage -0.03 Input Leakage Output Leakage Reset Input Current Supply Current -2 -2
0.4 VCC 0.8 2 2 -180 55 40 30 20 15 12 10 16
IOH= -2.0 mA IOH = -100 A IOL = +5 mA
35 25 20 15 9 7 1 5
Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 33 MHz [1] @ 25 MHz [1] @ 20 MHz [1] HALT Mode VIN = OV, VCC @ 33 MHz [1] HALT Mode VIN = OV, VCC @ 25 MHz [1] HALT Mode VIN = OV, VCC @ 20 MHz [1] STOP Mode VIN = OV, VCC [1]
ICC1 ICC2 IAL
Note:
Standby Current (HALT Mode)
Standby Current Auto Latch Current
-16
[1] All inputs driven to 0V, or Vcc and outputs floating.
7
Z86C93 CPS DC-4020-12
AC CHARACTERISTICS External Memory Read/Write Timing Diagram
R/W, /DM
19 12
20 13
Port 0
A8 - A15
16 21
Port 1
A0 - A7
2 3
D0 - D7 IN
9 10
A0 - A7
/AS
8 4 5 6 11
/DS (Read)
1
17
Port1
A0 - A7
14
D0 - D7 OUT
15 7
A0-A7
/DS (Write)
External Memory Read/Write Timing
8
Z86C93 CPS DC-4020-12
AC CHARACTERISTICS External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
33 MHz Min Max 15 20 96 15 TA = 0C to +70C 25 MHz 20 MHz Min Max Min Max 22 25 130 28 0 100 65 55 0 40 30 26 30 34 34 115 40 22 34* 35 35 45 35 35 45 35 5 15 20 10* 15* 25* 160 48 26 85 0 48 36 32 36 40 40 200 26 28 160 36 0 130 75 100
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30
Sym TdA(AS) ThAS(A) TdAS(DI) TwAS TdAZ(DSR) TwDSR TwDSW TdDSR(DI) ThDSR(DI) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDO(DSW) ThDSW(DO) TdA(DI) TdAS(DSR) TdDM(AS) TdDS(DM) ThDS(A) TdXT(SCR) TdXT(SCF) TdXT(DSRF) TdXT(DSRR) TdXT(DSWF) TdXT(DSWF) TsW(XT) ThW(XT) TwW
Parameter Address Valid To /AS Rise Delay /AS Rise To Address Hold Time /AS Rise To Data In Req'd Valid Delay /AS Low Width
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Float To /DS Fall (Read) 0 /DS (Read) Low Width 65 /DS (Write) Low Width 40 /DS Fall (Read) To Data in Req'd Valid Delay /DS Rise (Read) to Data In Hold Time /DS Rise To Address Active Delay /DS Rise To /AS Delay R/W Valid To /AS Rise Delay 0 25 16 12
/DS Rise To R/W Not Valid Delay 12 Data Out To /DS Fall (Write) Delay 12 /DS Rise (Write) To Data Out Hold Time 12 Address Valid To Data In Req'd Valid Delay /AS Rise To /DS Fall (Read) Delay /DM Valid To /AS Rise Delay /DS Rise To /DM Valid Delay /DS Rise To Address Valid Hold Time XTAL Falling to SCLK Rising** XTAL Falling to SCLK Falling** XTAL Falling to/DS Read Falling** XTAL Falling to /DS Read Rising** XTAL Falling to /DS Write Falling** XTAL Falling to /DS Write Rising** Wait Set-up Time Wait Hold Time Wait Width (One Wait Time) 30 15 15
Notes: When using extended memory timing add 2 TpC. Timing numbers given are for minimum TpC. * Typical value to be characterized (25 MHz). ** External clock drive.
9
Z86C93 CPS DC-4020-12
XTAL1
(External Clock Drive)
22 23
SCLK 24 25
/DS DSR (READ)
26
27
/DS DSW (Write)
XTAL/SCLK To DSR and DSW Timing
T1
T2
TW
TW
TW
T3
T1
XTAL1
SCLK
/AS
/DS 32 /WAIT
30
31
XTAL/SCLK To WAIT Timing (25 MHz and 33 MHz Devices Only)
10
Z86C93 CPS DC-4020-12
AC CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
T IN
4 6 5
IRQ N
8 9
Additional Timing
AC CHARACTERISTICS Additional Timing Table
33 MHz Min Max 30 10 75 1000 5 TA = 0C to +70C 25 MHz 20 MHz Min Max Min Max 42 11 75 3 TpC 8 TpC 100 70 5 TpC 3 TpC 1000 10 50 15 75 3 TpC 8 TpC 100 70 5 TpC 3 TpC 1000 10
No Symbol 1 2 3 4 5 6 7 8A 8B 9 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH
Parameter Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width
Units ns ns ns ns
Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3]
Timer Input High Width 3 TpC Timer Input Period 8 TpC Timer Input Rise & Fall Times 100 Interrupt Request Input Low Times 70 Interrupt Request Input Low Times 5 TpC Interrupt Request Input High Times 3 TpC
ns ns
Notes:
[1] [2] [3] [4] [5]
Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. Interrupt references request through Port 3. Interrupt request via Port 3 (P33-P31). Interrupt request via Port 30.
11
Z86C93 CPS DC-4020-12
AC CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1
3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
12
Z86C93 CPS DC-4020-12
AC CHARACTERISTICS Handshake Timing Table
No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf) Parameter Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time TA = 0C to +70C Min Max 0 0 40 70 40 0 TpC 0 70 40 40 Units ns ns ns ns ns ns ns ns ns ns ns Data Direction In In In In In In Out Out Out Out Out
(c) 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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